One type of image sensor is an active pixel sensor (APS). APS image sensors are typically fabricated using metal oxide semiconductor (MOS) processing technology, in particular for example Complementary Metal Oxide Semiconductor (CMOS) processing technology, and are typically referred to as (C)MOS image sensors or contact image sensors (CIS). CMOS image sensors sense light by converting incident radiation (photons) into electronic charge (electrons) via the photoelectric effect. CMOS image sensors typically include a photoreceptor (e.g. photodiode) and several CMOS transistors for each pixel.
Existing CMOS image sensors include, but are not limited to, three-transistor (3T) and four-transistor (4T) pixel implementations. Pixel implementations with more than four transistors have also been implemented. The pixel circuits in this type of image sensors typically include a source follower transistor that is used to buffer the photoreceptor voltage onto a column line.
An existing pixel configuration is illustrated in FIG. 1. FIG. 1 illustrates, as an example only, a 4T pixel 10 for a CMOS image sensor. All transistors in the pixel are MOS transistors. The pixel 10 illustrated in FIG. 1 comprises a photoreceptor 11, in the example illustrated a pinned photodiode PPD, for converting impinging radiation into electronic charge. The pixel 10 furthermore includes a sample and hold transistor 12 for transferring charge generated by the photoreceptor 11 towards a sense node in the form of a floating diffusion 16, a reset transistor 13 for resetting the sense node to a starting value, a source follower transistor 14 for converting the transferred charge into a voltage and a select transistor 15 for actually putting that voltage onto a column line.
FIG. 2 shows a cross-section of such classical 4T or pinned photodiode pixel. In a substrate 20, for example a substrate of a first type, e.g. p-type, a photoreceptor, e.g. a photodiode 11, is provided. This photodiode 11 may for example be a lowly doped region of a second type different from the first type, such as a region with an implanted dopant dose of 1016/cm3 or lower, e.g. an n-region. The photodiode 11 is pinned by means of a pinning layer 21, for example a highly doped region of the first type, such as a region with an implanted dopant dose of 1018/cm3 or higher, e.g. a p+ region. The sample and hold transistor 12 is formed by a control electrode, e.g. a transfer gate 22, formed on an insulating layer 23 on a major surface of the substrate 20. A first major electrode of the sample and hold transistor 12 is formed by the photodiode region 11, and a second major electrode of the sample and hold transistor 12 is formed by the floating diffusion 16. The reset transistor is formed by a control electrode, e.g. a reset gate 24, formed on the insulating layer 23 of the major surface of the substrate 20. A first major electrode of the reset transistor 13 is formed by the floating diffusion 16, and a second major electrode of the reset transistor 13 is formed by a highly doped contact region 25 of the second type, such as a region with an implanted dopant dose of 1018/cm2 or higher, e.g. an n+ region. The contact region is connected to a power supply VDD. The floating diffusion 16 is connected to a control electrode, e.g. gate, of the source follower transistor 14, of which a first major electrode, e.g. a drain, is connected to the power supply VDD as well. The second major electrode, e.g. source, of the source follower transistor 14 is connected to a first major electrode, e.g. the drain, of the select transistor 15, and the second major electrode, e.g. the source, of the select transistor 15 is connected to an output bus 26.
At the bottom of FIG. 2, two (idealized) potential diagrams of the structure illustrated are shown: one for an empty photodiode 11 and one for a completely filled photodiode 11. It is to be noted that the positive direction of the potential is indicated downwards.
The first potential diagram shows the situation for the case where the floating diffusion 16 is reset, and the pinned photodiode 11 is completely empty. The second potential diagram has a completely filled photodiode 11, while the floating diffusion 16 is still in the reset mode. As can be understood, the possible charge content of the pinned photodiode 11 is proportional to the area of the photodiode 11 multiplied by the depth of the pinned photodiode 11. The latter is defined as the potential difference between the bottom of the pinned photodiode and the potential underneath the transfer gate 22.
This “possible charge content” of the pinned photodiode 11 is also called the full-well capacity of the pinned photodiode 11. It is the largest charge the pixel can hold before going into saturation. In simple terms, this full well capacity is defined by the width of the pinned photodiode (very often close to the width of the pixel), the length of the pinned photodiode (very often close to the length or height of the pixel), and the depth of the photodiode (very often close to 1.5 V). The depth of the photodiode is the difference in voltage between the fully depleted photodiode and the barrier towards the floating diffusion, being the voltage underneath the transfer gate 22.
The full-well capacity of image sensors in general, and of the pinned photodiodes in particular, plays a dominant role in the definition of the dynamic range of imagers. Especially in digital still applications in combination with small pixels, the dynamic range may be low.
EP1178674 describes a solid state pickup device and camera system in which unit pixels each including a photodiode, a transfer transistor for transferring the signal of the photodiode to a floating node, an amplifying transistor for outputting the signal of the floating node to a vertical signal line, and a reset transistor for resetting the floating node are arranged in a matrix form. A P-type MOS transistor is connected between a wire to which a main electrode of the reset transistor at the opposite side to the floating node is connected, and a driving circuit for selectively applying a reset voltage to the wire. When a reset voltage is output from the driving circuit, the P-type MOS transistor is conducting to thereby apply the reset voltage to the wire. The reset voltage is supplied through the reset transistor to the floating node to thereby reset the potential of the node concerned. On the other hand, when no reset voltage is output from the driving circuit, the channel voltage of the P-type MOS transistor is applied to the wire. When the reset transistor is conducting, the potential of the floating node is determined by the channel voltage of the P-type MOS transistor, and thus is not equal to 0 V. Therefore, leakage of charges from the floating node through the transfer transistor to the photoelectrical conversion element can be prevented.